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AR# 35241 LogiCORE IP XAUI v9.2 - Timeout seen in some Virtex-5 FPGA Example Design Timing Simulations

Description

When running timing simulation with the XAUI Virtex-5 FPGA example design, timeouts are sometimes seen.

Solution

This can been seen due to timing failures on the XGMII interface which is not constrained. This interface will typically be connected to internal logic when used in a customer's system.

Actions

AR# 35241
Date Created 04/14/2010
Last Updated 04/14/2010
Status Active
Type
Devices
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
Tools
  • ISE Design Suite - 12.1
IP
  • XAUI
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