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AR# 35244

LogiCORE IP 10-Gigabit Ethernet MAC v10.1 - Release Notes and Known Issues for ISE Design Tools 12.1

Description

This Answer Record contains the Release Notes for the LogiCORE IP 10-Gigabit Ethernet MAC v10.1 core, which was released in ISE design tools12.1, and contains the following information:

  • New Features
  • Bug Fixes
  • Known Issues

For installation instructions, general CORE Generator software known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

New Features

  • 12.1 ISE software support
  • Spartan-6 FPGA support
  • Option added for DisablingControl Frame Length Check

Resolved Issues

  • (Xilinx Answer 34161) - LogiCORE IP 10-Gigabit Ethernet MAC v9.3 - The Virtex-6 FPGA Example Design MMCM instances can cause DRC errors
  • (Xilinx Answer 34783)-LogiCORE IP 10-Gigabit Ethernet MAC v9.3 - Virtex-6 Block RAM parameterization might result in memory collisions during simulation and erroneous operation
  • (Xilinx Answer 35261)-LogiCORE IP 10-Gigabit Ethernet MAC v9.3 and earlier - VLAN frame misclassified after pause frame

Known Issues

  • (Xilinx Answer 35835)- LogiCORE IP 10-Gigabit Ethernet MAC v10.1 and earlier - tx_underrun must be assert with tx_data_valid
  • (Xilinx Answer 35836)- LogiCORE IP 10-Gigabit Ethernet MAC - Timing errors seen when targeting Virtex-4 FPGAs
  • (Xilinx Answer 39537) - LogiCORE IP 10-Gigabit Ethernet MAC v10.1 - Timing Simulation targeting Virtex-6 devices reports RX_DATA isincorrect

Linked Answer Records

Child Answer Records

AR# 35244
Date Created 04/19/2010
Last Updated 05/20/2012
Status Active
Type Release Notes
Tools
  • ISE Design Suite - 12.1
IP
  • 10 Gigabit Ethernet Media Access Controller