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AR# 35248 MIG v3.4 Virtex-5 FPGA - All VHDL Example Design outputs using Synplify flow will fail in hardware

Description

Virtex-5 FPGA VHDL Example Designs output by MIG v3.4 do not function in hardware when synthesized using Synplicity. This is as a result of an issue in which the Synplicity tool does not initialize the BRAM that stores the Example Design address and command properly. Because the BRAM is not initialized, there is no data driven by the testbench. This affects all Virtex-5 FPGA MIG Example Designs output for the VHDL/Synplicity flow.

Solution

To work around this issue:
  • Generate the Example Design in Verilog and run the design through the Synplicity flow, or
  • Generate the VHDL design for the XST flow and rerun using XST

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

Actions

AR# 35248
Date Created 04/19/2010
Last Updated 05/20/2012
Status Active
Type Known Issues
Devices
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Less
IP
  • MIG
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