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AR# 35260 MIG Virtex-6 DDR2/DDR3 - Clocking and Reset

Description

This section of the MIG Design Assistant will guide you to details on the clocking and reset for the Virtex-6 DDR3/DDR2 designs. Please select from the below options to find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

(Xilinx Answer 35242) - Clock Requirements

  • Includes information on the design's clocking scheme as well as changing the input clock frequency
(Xilinx Answer 33268) - Sharing MMCMs

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33268 MIG Virtex-6 DDR2/DDR3 - Is it possible to combine MMCMs to save MMCM resources in multi-controller designs? N/A N/A
35242 MIG Virtex-6 DDR2/DDR3 - Clock Requirements and Modifying the Input Clock Frequency N/A N/A

Actions

AR# 35260
Date Created 05/20/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG
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