We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35260

MIG Virtex-6 DDR2/DDR3 - Clocking and Reset


This section of the MIG Design Assistant will guide you to details on the clocking and reset for the Virtex-6 DDR3/DDR2 designs. Please select from the below options to find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


(Xilinx Answer 35242) - Clock Requirements

  • Includes information on the design's clocking scheme as well as changing the input clock frequency
(Xilinx Answer 33268) - Sharing MMCMs

Linked Answer Records

Associated Answer Records

AR# 35260
Date Created 05/20/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • MIG