1. INTRODUCTION

For the most recent updates to the IP installation instructions for this core, please go to:

www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements:

www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

This file contains release notes for the Xilinx LogiCORE IP Virtex-6 FPGA GTX Transceiver Wizard v1.5 solution. For the latest core updates, see the product page at:

http://www.xilinx.com/products/intellectual-property/V6_FPGA_GTX_Transceiver_Wizard.htm

2. NEW FEATURES

- ISE 12.1 software support
- New protocol files added: HD-SDI, Serial RapidIO Generation 2

3. SUPPORTED DEVICES

- xc6vcx75t, xc6vcx130t, xc6vcx195t, xc6vcx240t, xc6vhx250t, xc6vhx255t,
xc6vhx380t, xc6vhx565t, xc6vlx75t, xc6vlx130t, xc6vlx195t, xc6vlx240t,
xc6vlx365t, xc6vlx550t, xc6vsx315t, xc6vsx475t

4. RESOLVED ISSUES

- Fixed CR 523129, 550149, 550151, 544164, 544159, 544158, 536786, 536659

5. KNOWN ISSUES

The following are known issues for v1.5 of this core at time of release:

- The transceiver attributes are not validated on the latest production silicon

The most recent information, including known issues, workarounds, and resolutions for this version is provided in the IP Release Notes Guide located at

www.xilinx.com/support/documentation/user_guides/xtp025.pdf

6. TECHNICAL SUPPORT

To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

7. OTHER INFORMATION

- Display Port, Fiber Channel 1G, 2G, 4G, OC48, SATA-I and SATA-II protocol files are not tested for compliance
- For Display Port protocol, set TX/RXPLL_DIVSEL_FB=2, TX/RXPLL_DIVSEL_REF=1, TX/RXPLL_DIVSEL_OUT=1
- For SATA-II protocol, set TX/RXPLL_DIVSEL_FB=2, TX/RXPLL_DIVSEL_REF=2, TX/RXPLL_DIVSEL_OUT=1
- The transceiver attributes of v1.5 version of this core support 2.01 silicon revision

8. CORE RELEASE HISTORY

Date By Version Description
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04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
04/24/2009 Xilinx, Inc. 1.1 Initial release
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