12.1 Known Issues
(Xilinx Answer 34674) 11.x/12.1 ChipScope IBERT - Virtex-6 FPGA GTX: CORE Generator does not list upper GTXE1 quads of SX475T and LX550T
(Xilinx Answer 31596) ChipScope Pro Analyzer- Can I use a BSCAN in my design when I insert ChipScope Pro Analyzer cores? How do I tell ChipScope Pro Analyzer to use a specific BSCAN primitive?
(Xilinx Answer 34581) 11.x ChipScope Pro - BUFG insertion is always enabled on the JTAG clock for the ICON core
(Xilinx Answer 35417) 12.1 ChipScope Pro - Virtex-6Q, Spartan-6Q and Spartan-6Q LX/LXT devices are not supported in ChipScope Pro Tools
(Xilinx Answer 34683) 11.x/12.x ChipScope, Virtex-6 - IBERT parameter sweep tests show errors in the middle of the eye
(Xilinx Answer 35418) 12.1 ChipScope Pro IBERT - "Error-it's been over 5 sec and can't receive a core update yet."
(Xilinx Answer 33701) 12.1/11.x ChipScope Pro IBERT, Virtex-6 - IBERT generation fails on Virtex-6 device when I enable 8 or more GTs
(Xilinx Answer 35420) 12.x/11.x ChipScope IBERT - Using LVDS_25 clock for system clock does not enable DIFF_TERM on input
(Xilinx Answer 35579) 12.1/11.5 ChipScope Pro - ATC2 Core - FATAL_ERROR:Pack:pks3eiobregrules.c:973:1.16 - The dual data rate register symbol...
(Xilinx Answer 35582) 12.1/11.5 ChipScope Pro ATC2, CORE Generator - "ERROR:sim - ATD_Drivers: Invalid value 'Individual'. Finished Regenerating.When I generate an ATC2 core with "Pin Edit Mode" set to 'Individual' I see the following errors in ChipScope Inserter - WARNING:sim:1"

12.2 Resolved Issues
(Xilinx Answer 34674) 11.x/12.x ChipScope, IBERT - Virtex-6 GTX, CORE Generator does not list upper GTXE1 quads of SX475T and LX550T
(Xilinx Answer 31596) ChipScope Pro Analyzer - Can I use a BSCAN in my design when I insert ChipScope Pro Analyzer cores? How do I tell ChipScope Pro Analyzer to use a specific BSCAN primitive?
(Xilinx Answer 35582) 12.1/11.5 ChipScope Pro ATC2 - CORE Generator "ERROR:sim - ATD_Drivers: Invalid value 'Individual'...."
(Xilinx Answer 35417) 12.1 ChipScope Pro - Virtex-6Q, Spartan-6Q and Spartan-6Q LX/LXT devices are not supported in ChipScope Pro Tools
(Xilinx Answer 34683) 11.x/12.x ChipScope, Virtex-6 - IBERT parameter sweep tests show errors in the middle of the eye
(Xilinx Answer 35418) 12.1 ChipScope Pro IBERT - "Error-it's been over 5 sec and can't receive a core update yet."

12.2 Known Issues
(Xilinx Answer 36576) 12.2 ChipScope IBERT - When I do not select the Implement Design option no implementation scripts are created
(Xilinx Answer 36577) 12.2 - Lab Tools, iMPACT, ChipScope Analyzer - Uninstall does not remove all files
(Xilinx Answer 36578) 12.1/12.2 ChipScope Pro Analyzer - cse_server.exe crashes after attempting to connect to the cable
(Xilinx Answer 33701) 12.1/11.x ChipScope Pro IBERT, Virtex-6 FPGA - IBERT generation fails on Virtex-6 device when I enable 8 or more GTs
(Xilinx Answer 35420) 12.x/11.x ChipScope IBERT - Using LVDS_25 clock for system clock does not enable DIFF_TERM on input
(Xilinx Answer 35579) 12.1/11.5 ChipScope Pro - ATC2 Core - FATAL_ERROR:Pack:pks3eiobregrules.c:973:1.16 - The dual data rate register symbol...
(Xilinx Answer 36906) 12.1/12.2 ChipScope Pro - IBERT - GTH line rates are limited to 6.6 Gb/s
(Xilinx Answer 37354) 12.2/12.3 ChipScope - IBERT - GTH - In the Analyzer the reset does always not set the error bit count to zero
(Xilinx Answer 37355) 12.2/12.3 ChipScope - IBERT - GTH - Parameter sweep is not supported

12.3 Resolved issues
(Xilinx Answer 36576) 12.2 ChipScope IBERT - When I do not select the Implement Design option no implementation scripts are created
(Xilinx Answer 36578) 12.1/12.2 ChipScope Pro - Analyzer - cse_server.exe crashes after attempting to connect to the cable
(Xilinx Answer 35579) 12.1/11.5 ChipScope Pro - ATC2 Core - FATAL_ERROR:Pack:pks3eiobregrules.c:973:1.16 - The dual data rate register symbol...
(Xilinx Answer 36906) 12.1/12.2 ChipScope Pro - IBERT - GTH line rates are limited to 6.6 Gb/s

12.3 Known issues
(Xilinx Answer 38340) 12.x ChipScope Pro, IBERT, Virtex-5, GTX - Line rate is displayed incorrectly and links are down
(Xilinx Answer 37354) 12.2/12.3 ChipScope - IBERT - GTH - In the Analyzer the reset does not always set the error bit count to zero
(Xilinx Answer 38015) 12.x ChipScope Pro, IBERT, Spartan-6, GTP - TX buffer is Off by default with far-end loopback
(Xilinx Answer 33701) 12.1/11.x ChipScope Pro - IBERT generation fails on a Virtex-6 device when I enable 8 or more GTs
(Xilinx Answer 35420) 12.x/11.x ChipScope IBERT - Using LVDS_25 clock for system clock does not enable DIFF_TERM on input
(Xilinx Answer 37354) 12.2/12.3 ChipScope - IBERT - GTH - In the Analyzer the reset does always not set the error bit count to zero
(Xilinx Answer 37355) 12.2/12.3 ChipScope - IBERT - GTH - Parameter sweep is not supported
(Xilinx Answer 39375) 12.3 Virtex-6 IBERT GTX - TXPOSTEMPHASIS MSB is not changed during sweep tests

12.4 Resolved Issues
(Xilinx Answer 38340) 12.x ChipScope Pro, IBERT, Virtex-5, GTX - Line rate is displayed incorrectly and links are down
(Xilinx Answer 37354) 12.2/12.3 ChipScope - IBERT - GTH - In the Analyzer the reset does not always set the error bit count to zero
(Xilinx Answer 38015) 12.x ChipScope Pro, IBERT, Spartan-6, GTP - TX buffer is Off by default with far-end loopback
(Xilinx Answer 37355) 12.2/12.3 ChipScope - IBERT - GTH - Parameter sweep is not supported
(Xilinx Answer 39375) 12.3 Virtex-6 IBERT GTX - TXPOSTEMPHASIS MSB is not changed during sweep tests

12.4 Known Issues
(Xilinx Answer 39125) Virtex-6 GTX IBERT - TX output swing lower than User Guide and Characterization Report
(Xilinx Answer 38861) Spartan-6 - IBERT - Coregen PAR Error: Timing not met
(Xilinx Answer 39515) 12.x ChipScope Spartan-6 ILA - When generating a design including an ILA I see "WARNING:NgdBuild:931 "
(Xilinx Answer 39512) 12.x ChipScope IBERT GTH - With DATAWIDTH=32 and more than one GT quad selected I see the error "ERROR:sim - runPar : IBERT:par: Timing for this design was not met. "
(Xilinx Answer 39238) 12.3 ChipScope ILA - Timing error found in Unconstrained Path report in ChipScope core
(Xilinx Answer 39647) 12.x ChipScope - ChipScope core generation when directory names are too long
(Xilinx Answer 39516) 12.4 ChipScope Pro IBERT Spartan-6 GTP - When generating my core I see "ERROR:PhysDesignRules:1859 "
(Xilinx Answer 39864)12.x ChipScope Pro - IBERT GTH - When Cable Speed is set to 3 MHz in Analyzer the IBERT Reset results in a incorrect value on the RX Bit counter
(Xilinx Answer 39756) 12.4 ChipScope IBERT - How to set the Virtex-6 GTH Transceivers in near-end PMA loopback?
(Xilinx Answer 40855) 12.x/13.1 ChipScope - IBERT - Virtex-6 GTX attribute TERMINATION_OVRD set incorrectly to TRUE

(Xilinx Answer 39871) 12.x/13.x ChipScope Pro - IBERT - Virtex-5 GTX - Core is not recognized by CS analyzer - UNIT:1_0 Unsupported (XSDB-512)