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AR# 35279

LogiCORE IP Tri-Mode Ethernet MAC v4.4, v4.4rev1 and v4.4rev2 - Release Notes and Known Issues for ISE 12.1 and ISE 12.2 software

Description

This Answer Record contains the Release Notes for the LogiCORE IP Tri-Mode Ethernet MAC v4.4 Core (released in theISE 12.1 software), v4.4 rev1 (released in ISE 12.2), and v4.4 rev2 (released as a patch below),and includes the following:
  • New Features
  • Resolved Issues
  • Known Issues
For installation instructions, general CORE Generator software known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

New Features
  • ISE 12.1 software support
  • QPro Virtex-6 FPGA Hi-Rel support
  • QPro Spartan-6 FPGA Hi-Rel support
  • QPro Virtex-5 FPGA Hi-Rel support
  • Support added for reduced TX IFG
Resolved Issues in v4.4 and later
  • (Xilinx Answer 33769) LogiCORE IP Tri-Mode Ethernet MAC v4.3 - CE incorrectly timed for DDR primitives in Spartan-6 FPGA designs
  • (Xilinx Answer 33771) LogiCORE IP Tri-Mode Ethernet MAC v4.3 - Spartan-3 FPGAIDDR not correctly inferred when using RGMII
  • (Xilinx Answer 33772) LogiCORE IP Tri-Mode Ethernet MAC v4.3 - Update needed to I/O logic for Spartan-6 FPGA RGMII designs
  • (Xilinx Answer 33416) 11.3 NetGen - NetGen assigns incorrect value to SIM_DEVICE attribute causing simulation failure
Resolved Issues in v4.4 rev1 and later

  • (Xilinx Answer 35337)LogiCORE IP Tri-Mode Ethernet MAC - Meeting RGMII setup and hold when targeting Spartan-6 FPGAs
  • (Xilinx Answer 34764)LogiCORE IP Tri-Mode Ethernet MAC v4.4 and earlier- Virtex-6 FPGA block RAM parameterization might result in memory collisions during simulation and erroneous operation
  • (Xilinx Answer 35065)LogiCORE IP Tri-Mode Ethernet MAC v4.4 and earlier- Spartan-6 FPGA block RAM parameterization might result in memory collisions during simulation and erroneous operation
Resolved Issues in v4.4 rev2

  • In 12.2 and later with the rev2 patch, RGMII is now supported in Spartan-6 FPGA without a DCM; see the download below.
Known Issues in v4.4 rev2
  • (Xilinx Answer 33111) LogiCORE IP Ethernet Statistics v3.x and LogiCORE IP Tri-Mode Ethernet MAC v4.x - Error regarding no matching objects found seen in the example design timing simulation
  • (Xilinx Answer 35336)LogiCORE IP Tri-Mode Ethernet MAC - Meeting GMII setup and hold times when targeting Spartan-6 FPGAs
  • (Xilinx Answer 39138) LogiCORE IP Tri-Mode Ethernet MAC v4.4rev2 and earlier - 11 byte IFG transmitted when core generated for Full Duplex only
Download Rev2 update

To obtain an updated Spartan-6 RGMII example design that does not use a DCM , apply the following patch to the Xilinx ISE 12.2 or later software installation:
http://www.xilinx.com/txpatches/pub/swhelp/coregen/ar35279_tri_mode_eth_mac_v4_4_rev2.zip

Install the patch by extracting the contents of the ".zip" archive to the root directory of the Xilinx ISE 12.2 or later software installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.

After installing the patch, regenerate the Tri-Mode Ethernet MAC v4.4 LogiCORE in CORE Generator. For further information on finding the Xilinx install and using environment variables, see (Xilinx Answer 11630).

NOTE: You might be required to have system administrator privileges to install the patch if you do not have write permissions to the Xilinx Install directory.

Linked Answer Records

Child Answer Records

AR# 35279
Date Created 04/19/2010
Last Updated 05/22/2012
Status Active
Type Release Notes
Tools
  • ISE Design Suite - 12.1
IP
  • Tri-Mode Ethernet MAC