UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35289

MIG v3.4, Spartan-6 FPGA LPDDR - When running the LPDDR design the traffic generator stops sending commands after long write bursts

Description

For Spartan-6 FPGA LPDDR designs, the traffic generator used in the MIG example design may stop sending commands after long write bursts. 

This only affects the example design and not the user design.

Solution

This is due to a known issue in the traffic generator code and the use of the mcb_full signal. 

To correct this, the mcb_wr_full signal should be used instead.

This issue is resolved in the next release of the MIG controller 3.5, available with ISE Design Suite 12.2.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 35289
Date Created 04/19/2010
Last Updated 08/14/2014
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
IP
  • MIG