This is due to a known issue with the Virtex-4 FPGA VHDL RLDRAMII design; this issue does not occur with the Verilog design. This issue is resolved in the next release of MIG v3.5 due out in ISE Design Suite 12.2.
To resolve this issue, constant delay parameters can be changed in sim_tb_top.vhd from "0.00 ns" to "0.01 ns".
Existing code:
constant TPROP_PCB_CTRL : time := 0.00 ns; --CTRL delay value
constant TPROP_PCB_QK : time := 0.00 ns; --QK delay value
constant TPROP_PCB_DATA : time := 0.00 ns; --DATA delay value
constant TPROP_PCB_DATA_RD : time := 0.00 ns; --READ DATA delay value
Modify above parameters as follows:
constant TPROP_PCB_CTRL : time := 0.01 ns; --CTRL delay value
constant TPROP_PCB_QK : time := 0.01 ns; --QK delay value
constant TPROP_PCB_DATA : time := 0.01 ns; --DATA delay value
constant TPROP_PCB_DATA_RD : time := 0.01 ns; --READ DATA delay value