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AR# 35297

11.4 EDK, MPMC v5.04.a - SDMA does not commit last cycle of data to memory during RX

Description

When using MPMC with SDMA, the last beat of data is not committed to memory during receives (write to memory) of the data buffer. How do I resolve this issue?

Solution

This issue is fixed in MPMC v6.00.a, to be released in EDK 12.1.
AR# 35297
Date Created 09/24/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • More
  • Virtex-4 SX
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
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Tools
  • EDK - 10.1 sp2
  • EDK - 10.1
  • EDK - 10.1 sp1
  • More
  • EDK - 10.1 sp3
  • EDK - 11.1
  • EDK - 11.2
  • EDK - 11.3
  • EDK - 11.4
  • EDK - 11.5
  • Less
IP
  • Multi-Port Memory Controller (MPMC)