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AR# 35300

11.4 EDK, MicroBlaze - Processor stall occurs when TLB set to inhibit caching


If MicroBlaze v7_02_d is configured with a MMU, writeback caches and c_dcache_always_used=1, and MicroBlaze can stall if the a TLB is configured as inhibit caching. How do I resolve this issue.


To work around this issue, changing any of above settings should prevent the stalls.

This issue is fixed in MicroBlaze_v7_03_a, to be released in EDK 12.1.

AR# 35300
Date Created 04/19/2010
Last Updated 04/19/2010
Status Active
Type General Article
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