We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

# AR# 35308

## Description

Why am I seeing the minimum clock calculation show a larger clock-to-out delay on a Clock Modifying Block (CMB) than I see in the maximum clock calculation?

## Solution

CMBs can use feedback to deskew the clocks.The path that is used as the feedback is larger for maximum clock calculations and smaller for minimum clock calculations.

The clock going out of the CMB is being phase matched with these delays and that is how we accomplish the 'deskewing' effect.The phase matching is modeled by subtracting the delay of the feedback path from the clock path.Therefore, on a minimum clock path calculation you will see a smaller negative number than you will for the maximum clock path calculations.

An example of a Maximum clock path calculation:
Maximum Clock Path at Slow Process Corner: clk_pin to DAC_SPI_controller_i0/out_ddr_flop_spi_clk_i0/ODDR_inst
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
D12.I Tiopi 0.707 clk_pin
clk_pin
clk_gen_i0/clk_core_i0/clkin1_buf
BUFGCTRL_X0Y2.I0 net (fanout=1) 0.855 clk_gen_i0/clk_core_i0/clkout1
BUFGCTRL_X0Y2.O Tbgcko_O 0.092 clk_gen_i0/clk_core_i0/clkout2_buf
clk_gen_i0/clk_core_i0/clkout2_buf
OLOGIC_X1Y27.CLK net (fanout=66) 1.616 clk_tx
------------------------------------------------- ---------------------------
Total -0.477ns (-3.803ns logic, 3.326ns route)

An example of aMinimumclock path calculation:
Minimum Clock Path at Fast Process Corner: clk_pin to DAC_SPI_controller_i0/out_ddr_flop_spi_clk_i0/ODDR_inst
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
D12.I Tiopi 0.320 clk_pin
clk_pin
clk_gen_i0/clk_core_i0/clkin1_buf
BUFGCTRL_X0Y2.I0 net (fanout=1) 0.358 clk_gen_i0/clk_core_i0/clkout1
BUFGCTRL_X0Y2.O Tbgcko_O 0.033 clk_gen_i0/clk_core_i0/clkout2_buf
clk_gen_i0/clk_core_i0/clkout2_buf
OLOGIC_X1Y27.CLK net (fanout=66) 0.688 clk_tx
------------------------------------------------- ---------------------------
Total -0.417ns (-1.802ns logic, 1.385ns route)

If you are using a Virtex-6 or a Spartan-6 and newer devices, then the Timing Report (TWR) uses Multi-corner Multi-node timing analysis. This will produce four different timing numbers in the actual report:

Maximum Clock Path at Slow Process Corner: clk_pin to DAC_SPI_controller_i0/out_ddr_flop_spi_clk_i0/ODDR_inst
...
Minimum Clock Path at Slow Process Corner: clk_pin to char_fifo_i0/BU2/U0/grf.rf/rstblk/rd_rst_asreg
...
Maximum Clock Path at Fast Process Corner: clk_pin to lb_ctl_i0/debouncer_i0/meta_harden_signal_in_i0/signal_meta
...
Minimum Clock Path at Fast Process Corner: clk_pin to DAC_SPI_controller_i0/out_ddr_flop_spi_clk_i0/ODDR_inst