UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35324

LogiCORE Endpoint v3.7 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1

Description

This Release Notes and Known Issues Answer Record is for the LogiCORE Endpoint v3.7 for PCI Express, released in ISE Design Suite 12.1, and contains the following information:

  • General Information
  • New Features
  • Bug Fixes
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:


http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

New Features

  • ISE 12.1 software support

Resolved Issues

CR 432372: Core not transitioning from L1 to L0 to send a Completion.
Problem fixed (Virtex-5 only issue) where if the core received a Configuration Read/Write to Extended Configuration Space which is implemented by the user, and the core is directed to L1 before the user can respond with a Completion, then the Completion might not be sent until the core is transitioned to L0.

CR 438168: Virtex-5 x4 core might only wait 5 microseconds between ASPM L1 requests.
Problem fixed where if ASPM L1 Entry is enabled and the host rejects a core request to move into Active State L1, the core might only wait 5 microseconds before sending another request to move into Active State L1.
The specification states that an endpoint should wait at least 10 microseconds before re-initiating a request.

CR 454066: MSI selection not including 256 Vector MSI.
Problem fixed where GUI drop-down menu was not listing 256 vector MSI in the menu options.

CR 451548: MSI selection not propagating to parameter on the Wrapper.
Problem fixed where GUI drop-down menu selection was not propagating to the parameter on the PCI Express wrapper.

CR 480237: Updated simulation models to user SecureIP.
The simulation scripts have been updated to include SecureIP models instead of smartmodels.

CR 511335: Calibration Block updated.
The Calibration Block for the 1-lane, 2-lane, and Virtex-4 FXT designs have been updated.

CR 446720: SKP Ordered Sets generation intervals greater than Specification limit.
Issue resolved where under certain traffic conditions, the 8-lane core might generate SKP ordered sets at intervals greater than the specification limit of between 1180 and 1538 symbol times.

CR 531527: GT PLL settings updated.
The GTT PLL settings have been updated, as the current settings are out of spec.

Known Issue

(Xilinx Answer 40817) - LogiCORE Endpoint v3.7 for PCI Express - VCS simulations fail when using ISE Design Suite 13.1.
- Back Annotated Timing.
Back annotated timing or post-PAR functional netlist simulation run times can be extremely large.
This problem is primarily due to millisecond timeout counters in the physical layer link-training protocol.

- Timing closure with the LogiCORE Endpoint for PCI Express 8-lane Core.
Timing closure with the 8-lane 64-bit Endpoint core might require multiple PAR seeds or floorplanning.
Using Multi-Pass Place and Route (MPPR), you can use multiple cost tables to meet timing.
For more information on using MPPR, see the "Development System Reference Guide" in the Software Manuals at:

http://www.xilinx.com/support/library.htm

You might also need to floorplan and add advanced placement constraints for both your design and the 8-lane 64-bit Endpoint Core to meet timing.

- Timing closure with the LogiCORE Endpoint for PCI Express 4-lane Core.
Timing closure with the 4-lane 32-bit Endpoint core might require multiple PAR seeds or floorplanning.
Using Multi-Pass Place and Route (MPPR), you can use multiple cost tables to meet timing.
For more information on MPPR, see the "Development System Reference Guide" in the Software Manuals at:

http://www.xilinx.com/support/library.htm

You might also need to floorplan and add advanced placement constraints for both your design and the 4-lane 32-bit Endpoint Core to meet timing.

- Programmed Power Management and Active State Power Management.
Not supported in Virtex-4 devices.
Impact: PCI Express link cannot be driven to non-D0 Power Managed state.
The core transmitter cannot be driven to L0s and PCI Express link cannot be driven to L1 as part of Active State Power Management.
Work-around: None.

- The core does not implement "Loopback Slave".
The "Loopback Slave" mode is mainly used for verification and test, and has no impact on normal link operation.
Impact: The core cannot be put into "Loopback Slave" mode.
Work-around: None.

- MPS change results in lost ACK/NAK from core.
Changing the Maximum Payload Size might result in core failing to ACK or NAK outstanding TLPs when upstream bandwidth is fully utilized.
Impact: Can result in TLPs being resent unnecessarily.
Work-around: Host should not change MPS when there is downstream traffic that has not been acknowledged by the core.

- Link training failure due to excessive clock skew.

CR 513856

Training might fail on 8-lane and 4-lane 32-bit designs due to excessive clock skew on paths from DCM to BUFGs.
To prevent this, ensure all BUFGs are within the same quad.
Any cascaded BUFGs should be in the neighboring quad.

Work-around: Ensure all BUFGS are within the same quad.

- (Xilinx Answer 64156) - x1/x4 - 64-bit Interface Support

Revision History

04/03/2015 - Added (Xilinx Answer 64156)
03/01/2011 - Added (Xilinx Answer 40817)
04/23/2010 - Initial Release

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
40817 LogiCORE Endpoint v3.7 for PCI Express - VCS simulations fail when using ISE Design Suite 13.1 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40817 LogiCORE Endpoint v3.7 for PCI Express - VCS simulations fail when using ISE Design Suite 13.1 N/A N/A
AR# 35324
Date Created 04/20/2010
Last Updated 06/09/2015
Status Active
Type Release Notes
Devices
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-4 FX
Tools
  • ISE Design Suite - 12.1
IP
  • Endpoint for PCI Express (Soft-IP)