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AR# 35336

LogiCORE IP Tri-Mode Ethernet MAC - Meeting GMII setup and hold times when targeting Spartan-6 FPGAs


When targeting a Spartan-6 FPGA and using a GMII interface, theucf offset constraints for the GMII receiver inputsare currently commented out. The IEEE 2 ns setup 0 ns hold time is not met. The clock-data relationship of your specific design based on the connecting PHYand PCB layout should be investigated to see exact window that is needed. The window may not need to be as small as the IEEE 2 ns window specification.


If the required timing for your design cannot be met with the IDELAY interface, using a DCM to adjust the clock to data relationship could be considered.
AR# 35336
Date Created 04/28/2010
Last Updated 12/15/2012
Status Active
Type General Article