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AR# 35338

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII - Meeting GMII setup and hold times on an external interface when targetting Spartan-6 FPGAs


TheEthernet 1000BASE-X PCS/PMA or SGMII core is most commonly used with an internal GMII interface toconnect toa MAC or other user logic internal to the FPGA.There are some user applications where an external GMII interfaceto an external MAC or other logic is needed.When targeting a Spartan-6 FPGA, theucf offset constraints for the GMII inputsare currently commented out or missing.The IEEE 2 ns setup 0 ns hold time is not met.The clock-data relationship needed for your specific design should be investigated to see theexact window that is needed. The window might not need to be as small as the IEEE 2 ns window specification.


If the required timing for your design cannot be met with the IDELAY interface, using a DCM to adjust the clock to data relationship could be considered.
AR# 35338
Date Created 04/29/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • ISE Design Suite - 12.1
  • ISE Design Suite - 11.5
  • Ethernet 1000BASE-X PCS/PMA or SGMII