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AR# 35353

Serial RapidIO v5.4 - ML505 Example Design will not work when generated in VHDL


The ML505 Example Design in v5.4 or the Serial RapidIO Core will not work in hardware when generated in VHDL.


This is due to the srio_gt_wrapper_v5_1x.vhd file using the incorrect GT within the Tile. As the file is setup to use GT0 instead of GT1, the GT's are not connected to the correct SMA output as documented in (Xilinx Answer 29159). This can be fixed manually by modifying the file or by generating the example design in Verilog. This issue is fixed in v5.5 of the Core and later.
AR# 35353
Date Created 04/22/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Serial RapidIO