We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35371

Aurora 64B/66B v4.1 - Release Notes and Known Issues for ISE Design Suite 12.1


This Answer Record contains the Release Notes for the Aurora 64B/66B v4.1 Core, released in ISE DesignSuite 12.1, and includes the following:

  • New Features
  • Bug Fixes
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:


New Features

  • ISE 12.1 software support
  • Virtex-5 QPro/Virtex-6 QPro/HXT device family support
  • Removed license for the core from v4.1, pre v4.1 cores still need license
  • GUI modified to two pages

Bug Fixes

  • Removed deprecated -t switch from implementation script for PAR
  • Updates to Virtex-6 FPGA PLL rates
  • Defeatured values 1 through 4 for CLKFBOUT_MULT settings of MMCM

Known Issues

  • Virtex-6 FPGA solutions are pending for hardware validation
  • Virtex-6 HXT/GTH FPGA support is for verilog only
  • Virtex-6 HXT/GTH FPGA max lanes supported is 8 lanes
  • Virtex-6 HXT/GTH FPGA selection of quads should be consecutive
  • Virtex-6 FPGA Used quads have to be adjacent
  • Virtex-5 FPGA XQ5VFX200TFF1738 package is not supported
AR# 35371
Date Created 04/23/2010
Last Updated 05/19/2012
Status Active
Type Release Notes
  • Virtex-5 FXT
  • Virtex-5 TXT
  • Virtex-6 HXT
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • ISE Design Suite - 12.1
  • Aurora 64B/66B