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AR# 35372

Aurora 8B/10B v5.1 - Release Notes and Known Issues for ISE Design Suite 11.4

Description

This Answer Record contains the Release Notes for the Aurora 8B/10B v5.1 Core, released in ISE Design Suite 11.2, and includes the following: 

  • General Information 
  • New Features  
  • Bug Fixes 
  • Known Issues  

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: 
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

General Information 

The LogiCORE IP Aurora 8B/10B requires a license to generate and implement the core.

There is no charge for this license. 

To generate the license, visit the product page at: 
http://www.xilinx.com/products/ipcenter/aurora8b10b.htm

New Features

  • ISE 11.5 software support
  • Spartan-6 LXT device support
  • Virtex-6 -1L Lower power device support
  • Two-page GUI with label for each Transceiver
  • Timing simulation feature
  • NFC PAUSE value checking at RX FRAME_CHECK
  • Independent RESET module

Bug Fixes

  • Update MMCM minimum VCO frequency from 400 MHz to 600 MHz
  • De-feature GTX PLL feedback divider /1 for Virtex-6 & Virtex-6 -1L device family production silicon
  • Update charge pump attributes for Virtex-6 & Virtex-6 -1L device family GTX
  • The last 2 bytes of UFC message is corrupted when the UFC message size is greater than 14 bytes in 1 lane, 2 bytes design with user flow control interface along with simultaneous clock correction occurrence
  • Aurora 8B10B - Change transceiver label in GUI to XmYn format (instead of GTPDn format)
  • Virtex-5 FPGA Aurora 8b/10b v4.1 - PMA_INIT and INIT_CLK not explained
  • Aurora User Guide and Aurora Core: NFC and CC contention: lacking in documentation and wrong ACK answer from the core
  • Spartan-6 FPGA Early Release Aurora GTP clock Connection
  • Implement Script copies wrongly named ChipScope NGC files into results directory for Aurora 8B/10B v4.2

Known Issues

  • Virtex-6 FPGA solutions are pending hardware validation
  • GT REFCLK value is restricted to 500 MHz for Virtex-6 CXT device
  • Timing errors observed for designs with transceivers selected at extreme end of columns. Refer to the LogiCORE IP Aurora 8B10B v5.1 User Guide (UG353) for more details
  • Replacing Aurora 8B10B transceiver tile wrapper with GT wizards transceiver tile wrapper
  • The default transceiver tile wrapper generated from the GT wizards cannot be directly used in Aurora 8B10B as some ports are missing in the GTX Wizard v1.6.
    Generate a transceiver tile wrapper from GT Wizard with RXCHARIS_COMMA port selected and use that in Aurora 8B10B
  • The CORE Generator tool gives an incorrect message regarding licensing, "Full license for component < aurora_8b10b > allows you to use this component. This license does not give you access to source code implementing this component", even though the core delivers source code.
AR# 35372
Date Created 04/23/2010
Last Updated 02/19/2015
Status Active
Type Release Notes
Tools
  • ISE Design Suite - 11.4