NOTE: The root cause might be related to
(Xilinx Answer 34669). Please review this Answer Record before attempting the work-arounds below.
If you do not have on-board termination and require the use of the DIFF_TERM attribute for your clock, then you can see this problem. Without DIFF_TERM your clock can be incorrectly terminated and, therefore, will not be input to the device correctly; this will affect core operation resulting in the error message specified.
To work around this issue:
CORE Generator
Uncheck the "Implement Design" checkbox in the last CORE Generator customization screen. You can then modify the UCF file produced to add DIFF_TERM to the System Clock.
Example:
#-------------------------------------------------------------------------------------
# System Clock Timing Constraints and PIN LOCs (if applicable)
#-------------------------------------------------------------------------------------
NET "IBERT_SYSCLOCK_P_IPAD" LOC = AE30;
INST "U0/I_USE_SYSCLOCK.I_USE_SYSCLOCK_DIF_INPUT.U_SYSCLOCK_IBUFDS" IOSTANDARD = LVDS_25 | DIFF_TERM="TRUE";;
NET "IBERT_SYSCLOCK_P_IPAD" CLOCK_DEDICATED_ROUTE = FALSE;
NET "U0/ibert_sysclock" PERIOD = 312.5 MHz;
PIN "U0/U_IBERT_CORE/U_MA_DCLK_DIVIDER/mmcm_adv_inst.CLKIN1" CLOCK_DEDICATED_ROUTE = FALSE;
IBERT CORE Generator
After generating the core, open the NCD file in FPGA Editor (DIFF_TERM can be enabled here). Run BitGen again to regenerate the bit file, and then you will have a working core.