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AR# 35426

Virtex-6 FPGA Integrated Block for PCI Express - The v1.3, v1.3 rev 1, v1.4, and v1.4 rev 2 wrapper might not link train on startup when using ISE Design Suite 11.5 or later

Description

When I implement with the v1.3 or v1.3 rev 1 core targeting ES silicon, or the v1.4, v1.4 rev 2 core targeting production silicon, there are problems with link training and device recognition on some platforms.

On a cold start, the endpoint is not recognized by the system and the endpoint does not link train. 

If I issue a subsequent warm reset (Windows Restart), then the endpoint links train and is recognized.

Solution

In ISE Design Suite 11.5, the software automatically inserts the MMCM Calibration Circuit described in (Xilinx Answer 33849)

This circuit appears to cause issues with link training when using the v1.3 or v1.3 rev 1 wrapper on ES silicon, or the v1.4, v1.4 rev 2 wrapper on Production silicon.

This issue is fixed in the ISE Design Suite 12.1 release of the v1.5 wrapper for Production silicon.

For a solution for the v1.3 rev 1 core, see (Xilinx Answer 36008).

Revision History
06/08/2010 - Updated for v1.3 fix link.
05/03/2010 - Initial Release

Linked Answer Records

Associated Answer Records

AR# 35426
Date Created 05/03/2010
Last Updated 02/20/2015
Status Active
Type Known Issues
Devices
  • Virtex-6 LXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )