We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35468

Configuration - CRC error reported after disabling CRC checking


After I disable CRC checking in BitGen when generating the bit/bin file, INIT goes Low and iMPACT still reports:

"INFO:iMPACT:2217 - Error shows in the status register, CRC Error bit is NOT 0."
'3': Reading status register contents...
CRC error : 1

CRC checking is disabled, so why do I still see an error?


Disabling CRC checking in BitGen has two effects on a bit file:

  • It sets a bit in the COR register to disable the CRC calculation on incoming configuration data.
  • It inserts a default value in the CRC register writes that allows the check to pass. The value (0x0000DEFC) is loaded to the CRC register writes. This 0x0000DEFC appears twice in bit/bin, occupying the previous CRC value's position,just prior to loading thelast frame and again at the very end of the bit/bin. If the 16 LSB of this value - DEFC - are corrupted, a CRC error is triggered, so INIT will drive Low and the CRC_ERROR bit in the status register asserts to 1. The root cause is data corruption or signal integrity issues.

AR# 35468
Date 12/15/2012
Status Active
Type General Article
  • Spartan-3
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5 FXT
  • Spartan-3A
  • Spartan-3A DSP
  • Spartan-3AN
  • Spartan-3E
  • Spartan-6 LX
  • Spartan-6 LXT
  • Virtex-5Q
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • ISE Design Suite - 11.5
Page Bookmarked