AR# 35479

12.1 TRCE/Timing Analyzer - IODELAYE1 DATAOUT is being treated as a synchronous output

Description

My IODELAYE1 DATAOUT is being treated as a synchronous output.

However it is just a delayed output, so it should not be treated as a synchronous output:

Timing constraint: TS_clk_rd = PERIOD TIMEGRP "clk_rd" 5.716 ns HIGH 50%;
18360 paths analyzed, 12461 endpoints analyzed, 4 failing endpoints
4 timing errors detected. (4 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is   7.138ns.
--------------------------------------------------------------------------------
Slack:                  -0.711ns (requirement - (data path - clock path skew + uncertainty))
Source:               u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_idelay (OTHER)
Destination:          u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_iserdes (FF)
Requirement:          2.858ns
Data Path Delay:      1.372ns (Levels of Logic = 0)(Component delays alone exceeds constraint)
Clock Path Skew:      -2.162ns (1.438 - 3.600)
Source Clock:         u_rld_top/u_phy_top/clk_rd[1] rising at 0.000ns
Destination Clock:    u_rld_top/u_phy_top/clk_qk[1] falling at 2.858ns
Clock Uncertainty:    0.035ns
Clock Uncertainty:          0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ):   0.000ns
Discrete Jitter (DJ):       0.000ns
Phase Error (PE):           0.000ns
Maximum Data Path at Slow Process Corner: u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_idelay to u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_iserdes
Location               Delay type         Delay(ns) Physical Resource
Logical Resource(s)
--------------------------------------------------- -------------------
IODELAY_X1Y138.DATAOUT Tiodcko_DATAOUT       1.258   u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_idelay
u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_idelay
ILOGIC_X1Y138.DDLY     net (fanout=1)        0.001   u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/pd_iodly
ILOGIC_X1Y138.CLKB     Tisdck_DDLY_DDR       0.113   u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_iserdes
u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_iserdes
--------------------------------------------------- ---------------------------
Total                                        1.372ns (1.371ns logic, 0.001ns route)
(99.9% logic, 0.1% route)

Solution

This is a known issue and has been fixed in ISE Design Suite 12.3.

To work around the problem:

Place a TIG constraint on the path
Or
Remove the IODELAYE1 BEL from the PERIOD time group.

In both cases, the IODELAY DATAOUT path will not be analyzed as a synchronous starting point.

The latter work-around is preferred, however, it becomes complicated when the TIMEGRPs that the IODELAYE1s are being added to are tool-generated.

To work around this, most of the tool-generated constraints need to be replaced by user-defined constraints so that the IODELAYE1s can then be removed from the groups.

If the tool-generated constraints remain in the design (the IODELAYE1 BELs are left as members of these time groups), then these paths are incorrectly analyzed.

For example:

# Preexisting TNMs previously used with a PERIOD constraint

NET "tx_channel_1_rx_bufr_clk" TNM_NET = "tx_channel_1_rx_bufr_clk";

NET "tx_channel_2_rx_bufr_clk" TNM_NET = "tx_channel_2_rx_bufr_clk";

# Add IODELAYE1 BELs to a new TIMEGRP

INST "tx_channel_1/IODELAYE1_0" TNM = "iodelaye1s_chan1";

INST "tx_channel_2/IODELAYE1_0" TNM = "iodelaye1s_chan2";

# Build new TGs w/o the IODELAYE1 BELs

TIMEGRP "wa_tx_channel_1_rx_bufr_clk" = "tx_channel_1_rx_bufr_clk" EXCEPT "iodelaye1s_chan1";

TIMEGRP "wa_tx_channel_2_rx_bufr_clk" = "tx_channel_2_rx_bufr_clk" EXCEPT "iodelaye1s_chan2";

# Redefine these PERIODs using the TIMEGRPs that do not have the IODELAYE1 BELs

TS_tx_channel_1_rx_bufr_clk = PERIOD TIMEGRP "wa_tx_channel_1_rx_bufr_clk" 10 ns HIGH 50%;

TS_tx_channel_2_rx_bufr_clk = PERIOD TIMEGRP "wa_tx_channel_2_rx_bufr_clk" 10 ns HIGH 50%;

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AR# 35479
Date	12/02/2014
Status	Active
Type	General Article
Tools	ISE Design Suite - 12.1 ISE Design Suite - 12.2

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AR# 35479

12.1 TRCE/Timing Analyzer - IODELAYE1 DATAOUT is being treated as a synchronous output

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