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Timing constraint: TS_clk_rd = PERIOD TIMEGRP "clk_rd" 5.716 ns HIGH 50%;
18360 paths analyzed, 12461 endpoints analyzed, 4 failing endpoints
4 timing errors detected. (4 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 7.138ns.
--------------------------------------------------------------------------------
Slack: -0.711ns (requirement - (data path - clock path skew + uncertainty))
Source: u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_idelay (OTHER)
Destination: u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_iserdes (FF)
Requirement: 2.858ns
Data Path Delay: 1.372ns (Levels of Logic = 0)(Component delays alone exceeds constraint)
Clock Path Skew: -2.162ns (1.438 - 3.600)
Source Clock: u_rld_top/u_phy_top/clk_rd[1] rising at 0.000ns
Destination Clock: u_rld_top/u_phy_top/clk_qk[1] falling at 2.858ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_idelay to u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_iserdes
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
--------------------------------------------------- -------------------
IODELAY_X1Y138.DATAOUT Tiodcko_DATAOUT 1.258 u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_idelay
u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_idelay
ILOGIC_X1Y138.DDLY net (fanout=1) 0.001 u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/pd_iodly
ILOGIC_X1Y138.CLKB Tisdck_DDLY_DDR 0.113 u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_iserdes
u_rld_top/u_phy_top/u_phy_read_top/genblk25.nd_io_inst[1].gen_enable_pd.u_qdr_rld_phy_pd/qdr_pd_iserdes
--------------------------------------------------- ---------------------------
Total 1.372ns (1.371ns logic, 0.001ns route)
(99.9% logic, 0.1% route)
AR# 35479 | |
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Date | 12/02/2014 |
Status | Active |
Type | General Article |
Tools |
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