When an EDK design is created that does not include a MicroBlaze or PowerPC processor within the system, how can the PLBv46_PCIe BARs be correctly enabled? Without these BARs enabled, the PCIe is never able to access the PLBv46 bus interface. How do I create a standalone PLBv46_PCIe system?
Currently, the PCIe BARs (E0/E1/E2) are disabled on reset and cannot be changed without customization to the HDL source code.
To automatically enable the BARs on reset, you need to make the plbv46_pcie IP Core local to the EDK project. Then, edit the "plbv46_pcie_pkg.vhd" file in the pcore hdl/vhdl folder so that the constant C_BCR_INIT is set to zero. This enables the BARs and provides access from the plbv46_pcie to the plbv46 bus interface. Note that the PLBv46_PCIe also requires the BME bit to be set in order for completions to return to PCIe. This means that the root complex/driver must also not unset the BME bit from the PCIe interface.