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AR# 35493

Virtex-6 - 12.x Software Known Issues related to the Virtex-6 FPGA


This answer record describes the Known Issues for the Virtex-6 FPGA generation used with ISE Design Suite 12.


The following represent a collection of issues that have been identified in the12.x ISE Design Tools and are related to Virtex-6 FPGA. There might be issues which are present and are not listed here. If you discover an issue that is not on this list, please open a WebCase with Xilinx Technical Support.

It is strongly recommended that designs be re-synthesized (and IP cores re-implemented) when re-implementing for production using the software that has production status speed files for the target device. This ensures that the changes to DRCs, timing models, clock topologies, and other fixes in softwareare picked up.

All ISE Design Suite 12.x:


(Xilinx Answer 42444) Design Advisory - Virtex-6 FPGA designs using 18K/36K block RAM or 18K FIFO must be re-run through timing analysis


(Xilinx Answer 38132)Virtex-6 FPGA MMCM Design Advisory - MMCM BANDWIDTH attribute requirement
(Xilinx Answer 38133)Virtex-6 FPGA MMCM Design Advisory - Restriction for DIVCLK_DIVIDE value when Fclkin > 315 MHz

ISE Design Suite 12.3:


(Xilinx Answer 39029) Virtex-6 MMCM - Incorrect phase shift from MMCM when using negative phase shifts
(Xilinx Answer 34219) Virtex-6 MMCM - Cascaded MMCMs may not work in hardware

ChipScope Pro/IBERT

(Xilinx Answer 37355) 12.2/12.3 ChipScope - IBERT - GTH - Parameter sweep is not supported
(Xilinx Answer 32912) 11.2 ChipScope Analyzer - "ERROR:INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24"
(Xilinx Answer 35420) 12.x/11.x ChipScope IBERT - Using LVDS_25 clock for system clock does not enable DIFF_TERM on input
(Xilinx Answer 33599) 11.x ChipScope Pro - "csejtag - The application failed to start because libCseCore.dll was not found. Re-installing the application may fix this problem."
(Xilinx Answer 37354) 12.2/12.3 ChipScope - IBERT - GTH - In the Analyzer the reset does not always set the error bit count to zero


(Xilinx Answer 38104) MIG v3.6, Virtex-6 DDR3 - The GUI does not allow AXI RDIMM data width selection
(Xilinx Answer 37997) MIG v3.6 Virtex-6 DDR3 Multi-Controller - GUI only allows single controller generation for CXT -1 devices
(Xilinx Answer 37863) MIG v3.6, Virtex-6 Multi-Controller - Default bank selection for all FF1760 packages results in MAP error


(Xilinx Answer 37835) 12.2 MAP - MMCM calibration circuit not included when global optimization is turned on

GTX Transceiver

(Xilinx Answer 35681) Virtex-6 GTX Transceiver - MMCM fails to lock and TX/RXRESETDONE fails to assert

PCI Express

(Xilinx Answer 37963) Virtex-6 FPGA Integrated Block Wrapper v2.1 for PCI Express - VHDL Wrapper Not Available for v2.1 Release


ISE Design Suite12.2:

Block RAM

(Xilinx Answer 34859) Virtex-6 FPGA Block RAM Design Advisory - Address Space Overlap


(Xilinx Answer 35451) iMPACT 12.x - Removing Numonyx J3 (Rev D, F) indirect programming support for Virtex-6 in 12.2


(Xilinx Answer 35917) 12.1 Virtex-6 PlanAhead - When I import placement, BUFGDLL is not a supported primitive

ChipScope IBERT

(Xilinx Answer 36576) 12.2 ChipScope IBERT - When I do not select the Implement Design option no implementation scripts are created
(Xilinx Answer 34674) 11.x/12.1 ChipScope IBERT - Virtex-6 FPGA GTX: CORE Generator does not list upper GTXE1 quads of SX475T and LX550T
(Xilinx Answer 34683) 11.x/12.x ChipScope, Virtex-6 - IBERT parameter sweep tests show errors in the middle of the eye
(Xilinx Answer 36680) 12.2 CORE Generator - Generating an iBERT core fails with ERROR:sim - Unable to evaluate Tcl command

GTX Transceiver

(Xilinx Answer 37014) Virtex-6 GTX Transceiver: ERROR:MapLib:1226 - GTXE1 - DRC Error when POWER_SAVE is set incorrectly


(Xilinx Answer 36228) LogiCORE IP XAUI v9.1 and v9.1 rev1 - Virtex-6 GTX_POWER_SAVE needs to be updated to target ISE 12.2

Embedded Tri-mode Ethernet MAC Wrapper v1.4

(Xilinx Answer 36223) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.4 - When targeting SGMII or 1000BASE-X, DRC error is seen regarding GTX POWER_SAVE

Ethernet 1000BASE-X PCS/PMA or SGMII v10.5

(Xilinx Answer 36957) LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v10.5 - GMII setup/hold errors seen when targeting Virtex-6 HXT


(Xilinx Answer 33817) 12.2 EDK, MPMC v6.00.a, Virtex-6 - ERROR:ConstraintSystem:58 - Constraint does not match any design objects


ISE Design Suite12.1:

Aurora 64B/66B

(Xilinx Answer 35371) Aurora 64B/66B v4.1 - Release Notes and Known Issues for ISE Design Suite 12.1

Block RAM

(Xilinx Answer 34859) Virtex-6 FPGA Block RAM Design Advisory - Address Space Overlap


(Xilinx Answer 36274) 11.5, 12.1 Virtex-6 MMCM - MMCM does not lock after device startup andMMCM reset


(Xilinx Answer 36082) Virtex-6 SelectIO - DCI Cascade across non-continuous banks is supported in ISE software 12.2
(Xilinx Answer 36320) Virtex-6 - N-side pseudo-differential output driven by OSERDES does not toggle
(Xilinx Answer 35952) Config BitGen - UnusedPin option not pulling up unused I/Os in Virtex-6 devices


(Xilinx Answer 35574) 12.1 Project Navigator - The -mt (Enable Multi-Threading) option is greyed out in MAP and PAR Process Properties

Timing Simulation

(Xilinx Answer 35514) 12.1 - Timing simulation issue when targeting Virtex-6 devices


(Xilinx Answer 33942) 11.x iMPACT - When I add a Winbond SPI Flash for Indirect programming, I am prompted for a Data Width. Does Virtex-6 FPGA support x2 or x4 SPI?

Partial Reconfiguration

(Xilinx Answer 35399) 12.1 Virtex-6 FPGA Partial Reconfiguration - RAM contents not written correctly to Partial Bitfiles


(Xilinx Answer 35417) 12.1 ChipScope Pro - Virtex-6Q, Spartan-6Q, and Spartan-6Q LX/LXT devices are not supported in ChipScope Pro tools
(Xilinx Answer 33701) 12.1/11.x ChipScope Pro - IBERT - Virtex-6 - IBERT generation fails on Virtex-6 when I enable 8 or more GTs
(Xilinx Answer 34674) 11.x/12.x ChipScope, IBERT -Virtex-6 GTX, CORE Generator does not list upper GTXE1 quads of SX475T and LX550T
(Xilinx Answer 34683)11.x/12.x ChipScope, Virtex-6 - IBERT parameter sweep tests show errors in the middle of the eye

GTX Transceiver Wizard

(Xilinx Answer 34191) Virtex-6 FPGA GTX Transceiver Wizard - Attribute updates for production silicon

GTX Transceiver

(Xilinx Answer 35055) Virtex-6 FPGA GTX Transceiver - Automatic macro insertion for unused GTX Transceivers


(Xilinx Answer 34717) 12.1 EDK, MPMC v6.00.a- ERROR:EDK:1558 - PORT MPMC_Clk_Wr_I0 not found in mpd


(Xilinx Answer 35742) MIG v3.0-3.4 Virtex-6 DDR2 SDRAM - Incorrect timing on DDR2_RAS_N
(Xilinx Answer 35247) MIG v3.4 Virtex-6 DDR2/DDR3 - Fixed Pin-Out tool does not allow selection of VREF sites
(Xilinx Answer 35252) MIG v3.0-3.4 Virtex-6 DDR3 - REFCLK Frequency (IODELAYCTRL Reference clock) must be 300 MHz for interfaces running between 480-533 MHz
(Xilinx Answer 36503) MIG v3.4 Virtex-6 DDR3 - Cannot see phy_init_done go high in simulation

PCI Express

(Xilinx Answer 33834) Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Use of Component Name "core" Causes Implementation Failures using VHDL Flow
(Xilinx Answer 34009) Virtex-6 FPGA ML605 Board- PCI Express Link Will Not Train; Implementations for PCI Express Must Use the v1.3 Integrated Block Wrapper for PCI Express
(Xilinx Answer 34115) Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - WARNING:Xst:2016 - Found a loop when searching source

Tri-mode Ethernet MAC v1.4

(Xilinx Answer 33195) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Adjusting IDELAYs to meet GMII and RGMII setup and hold requirements

Revision History

09/24/2012 - Minor update; no change to content
07/18/2011 - Updated to include BRAM/FIFO issue
10/22/2010 - Added MMCM (Xilinx Answer 34219)
10/08/2010 - Updated for 12.3
08/02/2010 - Updated for 12.2 and added answer records for 12.1
05/04/2010 - Added GTX Transceiver (Xilinx Answer 35055) and Timing Simulation (Xilinx Answer 35514)
05/03/2010 - Initial 12.1 release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A
AR# 35493
Date Created 04/30/2010
Last Updated 09/25/2012
Status Active
Type Solution Center
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
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  • Virtex-6 LXT
  • Virtex-6 SXT
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  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3