UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35505

11.5 MAP - What are the various DRC checks that occur during the ISE implementation flow?

Description

DRC checks occur at various times during the ISE software implementation flow.

What sort of checks are done and when do they occur?

Solution


DRC checks are run at several key points in the implementation flow:

  • Early in the MAP process a DRC check is done on the logical design.
    This is referred to as Logical DRC and any errors or warnings will contain the string "LIT".
    Checks are done on the design connectivity such as checking for multiple drivers on each net and the properties on logical instances.
    The intent is to catch design issues as early as possible before any run time is wasted on the packing and placement of the design.
    At this point in the flow, the tools have no insight into the physical device and so there are limits to what can be checked.

  • Early in the Placement process some checks are run to determine the feasibility of the design from a placement point of view.
    The feasibility checks determine the feasibility of some of the physical structures (is the RPM macro too tall for the device?), the feasibility of a successful placement of the clock components (are all clock components placed with optimal connectivity?), and the feasibility of user constraints (are there unroutable connections created by constraints?).
    Various errors with the string "Place" can occur at this point.

  • At the end of MAP,  Physical DRC is run to confirm that all of the component configurations in the physical design (.ncd) do not violate any device rules.
    This is the first time that Physical DRC is run.
    It can also be run within FPGA Editor or as a command line tool (drc design.ncd).
    Physical DRC errors and warnings contain the string "PhysDesignRules".

  • Early in PAR, which routes the design, checks are made to warn about nets that have either no driver or no load.
    The router ignores these nets, as it is not possible to route a net that has either no driver or no load.

  • When BitGen is run, Physical DRC is run for a final time.
    Certain DRC issues that have generated warnings earlier are now upgraded to errors.
    The intent is to allow early incomplete revisions of a design to pass through the implementation tools with just warnings for certain faults, but to prevent a device from being programmed into hardware with those faults.
AR# 35505
Date Created 05/06/2010
Last Updated 01/07/2015
Status Active
Type General Article
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • Less