We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35514

12.1 - Timing simulation issue when targeting Virtex-6 devices


There is a timing simulation issue when targeting Virtex-6 devices.


In 12.1, MAP begins to automatically insert a macro that instantiates any unused GTXs for Virtex-6 FPGA designs, see(Xilinx Answer 35055).

Due to this macro insertion, NetGen creates a timing netlist with X_GTXE1 and X_STARTUP_VIRTEX6 blocks which causes intermittent failures in timing simulation. The macro insertion also requires a SecureIP license to simulate since GTXE1 is a hardIP.

To work around this issue,

1) Set the XIL_NETGEN_REMOVE_GTXE1 environment variable to 1. This variable removes all the auto-inserted primitives from the simulation netlist.

For more information about setting environment variables, see Xilinx Answer 11630.

2) Download and install the following patch:


This patch will remove references to the X_STARTUP_VIRTEX6 block in the SDF file. Use the readme.txt file for installation instructions.

3) Regenerate the timing netlist by using "ReRun" on the "Generate/Simulate Post-Place and Route Simulation Model" process, or by re-running the Netgen command used to generate the timing netlist.

For further help on this issue, please contact Xilinx Technical Support using one of the contact methods shown in the Support page.

Linked Answer Records

Associated Answer Records

AR# 35514
Date Created 05/03/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • ISE Design Suite - 12.1