UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35522

Virtex-5 GTP - PLL_DIVSEL_FB=3 is not allowed

Description

In the RocketIO Virtex-5 GTP Wizard v2.0 and later, some configurations are not allowed.

For example, in RocketIO GTP Wizard v1.10 I could choose a 125Mhz reference clock when the linerate is 3.75 Gbps.

However, in RocketIO GTP Wizard v2.0 a 125Mhz reference clock is no longer selectable in the GUI when linerate is 3.75 Gbps.

Why has this changed?

Solution

GTP performance has not yet been fully characterized when PLL_DIVSEL_FB=3.

It is not recommended to set PLL_DIVSEL_FB to 3.

AR# 35522
Date Created 05/03/2010
Last Updated 10/09/2014
Status Active
Type General Article
Devices
  • Virtex-5 LXT
  • Virtex-5 SXT