We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 35539

11.5 Place - How do I debug a "Place:543" error?


My design fails during placement with a "Place:543" error. The message is quite verbose and I am unable to understand it.

How can I make use of the information in this message to solve my problem?

"ERROR:Place:543 - This design does not fit into the number of slices available in this device due to the complexity of the design and/or constraints.

Unplaced instances by type: FF 100 (2.0%)

Please evaluate the following:

- If there are user-defined constraints or area groups:

Please look at the "User-defined constraints" section below to determine what constraints might be impacting the fitting of this design.
Evaluate if they can be moved, removed or resized to allow for fitting.
Verify that they do not overlap or conflict with clock region restrictions.
See the clock region reports in the MAP log file (*map) for more details on clock region usage.

- If there is difficulty in placing LUTs:
Try using the MAP LUT Combining Option (map lc area|auto|off).

- If there is difficulty in placing FFs:
Evaluate the number and configuration of the control sets in your design.

The following instances are the last set of instances that failed to place:

0. FF ImplementSampler.i_Sampler/i_input_mux/i_FB_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/count_d3<8>
1. FF ImplementSampler.i_Sampler/i_DDR2_top/U_0/u_mem_if_top/u_phy_top/phy_init_ras_n
2. FF ImplementSampler.i_Sampler/i_DDR2_top/U_0/u_mem_if_top/u_phy_top/u_phy_init/phy_init_done_r
3. FF i_EthernetInterface/i_eth_cosim_core/v5_emac_ll/client_side_FIFO_emac1/tx_fifo_i/wr_eof_pipe(1)

... (100 instances listed)

These instances could be impacted by the following constraints (the line IDs below correspond with the instances above):

User-defined constraints

31. < COMPGRP "CLKAG_ImplementCPRI.cpri_top_i/tx_clk_int.SLICE" LOC = SLICE_X0Y0:SLICE_X47Y19,SLICE_X48Y0:SLICE_X91Y19, SLICE_X0Y20:SLICE_X47Y39,SLICE_X48Y20:SLICE_X91Y39,SLICE_X0Y40:SLICE_X47Y59,SLICE_X4... >
32. < COMPGRP "CLKAG_ImplementCPRI.cpri_top_i/tx_clk_int.SLICE" LOC = SLICE_X0Y0:SLICE_X47Y19,SLICE_X48Y0:SLICE_X91Y19, SLICE_X0Y20:SLICE_X47Y39,SLICE_X48Y20:SLICE_X91Y39,SLICE_X0Y40:SLICE_X47Y59,SLICE_X4... >

... (more constraints listed)"


This message is printed when a design fails to fit, meaning that for some number of components no legal site placement was found. To understand the root cause of the failure, it is necessary to understand what components are failing to fit and then what pack/place restrictions apply to those components that make their fitting difficult. Once the restrictions are understood it is possible to look for ways of relieving restrictions.

Identifying the Logic Involved

The components listed in the Place:543 message are physical components whose name is usually not the same as the name of the instance in the logical netlist. Instead, the name is derived from an output net name. So, when trying to correlate a FF component back to the logical design, find the net with the same name in the logical design and then examine the FF driving it.

Identifying the Pack/Place restrictions on the Component

There are a number of restrictions that can apply to a FF component for example:

  • The FF might belong to an area group that is range constrained or constrained to a specific site.
  • If the FF is clocked by a global clock, it is likely to be range constrained by the clock placer so that no clock region has more clock domains than it can support (8 in Virtex-4, 10 in Virtex-5, 12 in Virtex-6 FPGA).
  • If the FF is clocked by a BUFIO or BUFR, then there will be clock region restrictions associated with that.
  • There are control set restrictions that prevent a FF from being packed into the same Slice component unless they share the same control set signals.
  • There are structural placement limitations. If the FF belongs to an RPM macro or a system macro, such as a carry chain structure, then the eventual placement needs to be able to accommodate the entire macro.

Look for Commonality Between the Components that Failed to Fit and Try to Relax the Placement Restrictions.

  • Are all the failing components FFs driven by the same clock? Check to see if the clock placer floorplanned the design with enough clock regions to fit that clock domain. Perhaps the clock placer's constraints can be tweaked to give the failing domain more space. For a common clock placement related issue, ee (Xilinx Answer 31150).
  • Do all of the failing components belong to the same very tall carry chain? Check the constraints on the carry chain logic and try to reduce the placement restrictions.
  • Are the failing components all FFs with different control sets? Check the map report to see if there is a high number of control sets. The map report calculates the number of FF sites that are unusable due to control set restrictions.
  • If the failing components are block RAM or some other large block, check to see if the clocks involved can reach a sufficient number of the site type needed.
AR# 35539
Date 05/07/2010
Status Active
Type General Article
  • Spartan-3
  • Spartan-3 XA
  • Spartan-3A
  • More
  • Spartan-3A DSP
  • Spartan-3AN
  • Spartan-3E
  • Spartan-6 LX
  • Spartan-6 LXT
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • Less