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AR# 35556

11.5 Route - Is there a way to lock the results of a successful route?

Description

I have a few critical paths in my design that aren't always routed optimally. Is there a way to lock the successful route results for these nets.

Solution

The routing from a successful implementation run can be locked using Directed Routing constraints. In order for this to work the net connectivity must remain the same and the relative location of all of the pins in net must be maintained. The constraints to reproduce the routing and relative pin location are captured in FPGA Editor using the Tools-->Direct Routing Constraints pull-down menu which opens the following form:

Using this form, nets can be chosen to capture routing constraints as well as place or pack constraints to control the relative pin location. Choose "Use Absolute Location Constraint" to lock the logic to its current location. Choose "Use Relative Location Constraint" to create an RPM macro that will maintain the relative pin locations in a movable macro. The constraints generated will be written to a UCF file and look like this:

NET "u_qdr2_top/QDR_PHY0/READ_INST/rd_data_fall[35]"
ROUTE="{3;1;5vlx50tff1136;7b83e2c2!-1;-78112;178824;S!0;-143;-1272!1;"
"-452;0!2;-1835;-3793!3;-843;-25723!4;0;-58872!5;11772;9812!5;0;-58872!6;"
"1608;-2712!7;5509;-10505!8;1454;-168!9;8284;-4212!10;183;-1295!11;5597;"
"-1143!12;-183;-2057!13;683;-488;L!14;404;8!16;843;24;L!}";
INST "u_qdr2_top/QDR_PHY0/READ_INST/Q_CQ_N_INST_18/MEM_INST[17].Q_INST/ISERDES_Q" LOC=ILOGIC_X0Y229;
INST "u_qdr2_top/QDR_PHY0/READ_INST/DLY_CAL_SM_INST_CQ_N_18/rd_data_fall_r_17" LOC=SLICE_X5Y88;
INST "u_qdr2_top/QDR_PHY0/READ_INST/DLY_CAL_SM_INST_CQ_N_18/rd_data_fall_r_17" BEL="CFF";
INST "u_qdr2_top/QDR_PHY0/READ_INST/PHY_EN_INST/rd_data_fall_out_35_mux00001" LOC=SLICE_X6Y64;
INST "u_qdr2_top/QDR_PHY0/READ_INST/PHY_EN_INST/rd_data_fall_out_35_mux00001" BEL="A6LUT";

These constraints constrain an ISERDES and its LUT and FF loads to their existing locations. The ROUTE constraint then reproduces the existing route in future revisions. The ROUTE constraint is not intended to be human readable.

Note: DIRT constraints are best used to constrain justa few critical nets. If overused they interfere with the router's ability to rip-up and re-route to accommodate other nets. There is also a problem associated with DIRT constraints due to the fact that the placer is not routing aware. The placer may place a component into a location where a routing path is blocked by a DIRT route. This most frequently occurs for Slice FFs using the direct inputs (AX, BX, CX, DX) where the input routing path is blocked by a DIRT route that uses a switchbox bounce off the pin used to access the direct input. The likelihood of this occurring goes up with the number of DIRT routes. This can be avoided with either PROHIBIT constraints or a combination of pack constraints that prevent the problem FF BEL site from being used.

AR# 35556
Date Created 05/07/2010
Last Updated 03/03/2013
Status Active
Type General Article
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