I have followed the directions shown in Xilinx Answer 35514 to remove all the auto-inserted primitives from the simulation netlist. However, when I launch a Post-Route (Timing) simulation in ISim, I encounter the following error:
ERROR: Can not find hierarchical name STARTUP_V6_PWRUP_GTXE1_ML_INSERTED in the current scope.
ERROR: (SdfError)While back annotating file "netgen/par/wave_gen_timesim.sdf", cell instance STARTUP_V6_PWRUP_GTXE1_ML_INSERTED not found in design.
Back-annotation is then unsuccessful and cannot properly perform a timing simulation of the design.
How can I resolve this issue?
This error can occur if theXIL_NETGEN_REMOVE_GTXE1 environment variable is set but the required patch (Step 2 in Xilinx Answer 35514) has not been properly installed. Please make sure you follow the patch installation instructions (readme.txt) properly.
For further assistance with this issue, please contact Xilinx Technical Support using the contact methods in the Support page.