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AR# 35591

Spartan-6 GTP Transceiver Wizard: tx_sync module does not use appropriate wait times


In some versions of the Spartan-6 FPGA GTP Transceiver Wizard, the tx_sync module generated when buffer bypass is enabled does not follow the timing outlined in the Spartan-6 FPGA GTP Transceiver User's Guide.


The code for the tx_sync module only holds TXENAPHASEALIGN for 32 cycles before asserting TXPMASETPHASE. It should hold it for 512 cycles. It is a simple matter to modify the code to extend the wait_before_setphase_counter_r register from 6 bits to10 bits, set the initialization value to 10 bits of 0, and to tie count_32_complete_r to bit 9 rather than bit 5. These modifications will increase the counter from 32 cycles to the appropriate 512 cycles.

These changes will be includedin v1.6 of the Spartan-6 GTP Transceiver Wizard.

AR# 35591
Date Created 05/10/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LXT
  • Spartan-6 FPGA GTP Transceiver Wizard