UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35594

12.1 EDK - The Spartan-6 SP605 board contains an incorrect clock pin location for the PCIe core

Description

The Spartan-6 FPGA SP605 board contains an incorrect pin location for the PCIe core.

Solution


Download and unzip the new SP605 fileXilinx_SP605_v2_2_0.zip, and replace the old onein the < XILINX_EDK >\board\Xilinx\boards\Xilinx_SP605\data directory.
This issue is resolved in 12.2.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34609 12.x EDK - Master Answer Record List N/A N/A
35593 12.1 EDK - What patches are currently available for EDK? N/A N/A
AR# 35594
Date Created 05/10/2010
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • EDK - 12.1
Boards & Kits
  • Spartan-6 FPGA SP605 Evaluation Kit