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AR# 35638

LogiCORE IP Video Scaler v2.1 - Why is the control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6?

Description

Why is the control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6 FPGA?

Solution

This is a known problem that only affects the pCore interface and is addressed in the next release of the Video On Screen Display IP.

You can contact Xilinx Technical Support for a way to work around this issue.

Please see (Xilinx Answer 31958) for a detailed list of LogiCORE IP Video Scaler Release Notes and Known Issues.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
31958 LogiCORE IP Video Scaler - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
31958 LogiCORE IP Video Scaler - Release Notes and Known Issues N/A N/A
AR# 35638
Date Created 05/28/2010
Last Updated 05/23/2014
Status Archive
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Virtex-6 CXT
  • More
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • Video Scaler