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AR# 35639

11.3 Schematic - Setting FF initialization in schematic does not work for FPGAs


If a Flip-flop schematic component is assigned an INIT attribute, the INIT value is recognized for CPLD designs. However, all FFs in an FPGA design are assigned to their default value (the INIT attribute is ignored).


In ISE Design Suite 11.1, the schematic netlisters were fixed to support the passing of the INIT attribute. However, due to the timing of the fix, only the CPLD libraries were updated to support he fix in ISE Design Suite 11.1.

The FPGA libraries were updated to support the INIT attribute in ISE Design Suite 11.4.

For previous versions of the software, the INIT attribute can be set on any Flip-flop using a User Constraints Format (UCF) file.

AR# 35639
Date 05/26/2014
Status Archive
Type General Article
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
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