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AR# 35641

LogiCORE IP Image Characterization v1.0 - When targeting Spartan-6 or Virtex-6 FPGA, why is the control register in big endian format, instead of little endian format as documented in the data sheet?

Description

When targeting Spartan-6 or Virtex-6 FPGA, why is the control register in big endian format, instead of little endian format as documented in the data sheet?

Solution

This is a known problem that only affect the pCore interface and is addressed in the Image Characterization v1.1.

Please see (Xilinx Answer 34574) for a detailed list of LogiCORE IP Image Characterization Release Notes and Known Issues.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34574 LogiCORE IP Image Characterization - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34574 LogiCORE IP Image Characterization - Release Notes and Known Issues N/A N/A
AR# 35641
Date Created 10/13/2010
Last Updated 05/23/2014
Status Archive
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Virtex-6 CXT
  • More
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • Image Characterization