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AR# 35673

12.1 - "ERROR:LIT:591/594/595 can affect DSP48 Macro v2.0 core standalone in 12.1"

Description

The DSP48 Macro v2.0 core can now produce errors in LIT due to new logical DRC checks added for Virtex-6 FPGA.

ERROR:LIT:595 - PCIN bus of DSP48E1 symbol
"BU2/U0/i_synth_option.i_synth_model/opt_vx6.i_uniwrap/i_primitive" can be sourced only by a PCOUT bus of a different DSP48E1 block.
ERROR:LIT:591 - ACIN bus of DSP48E1 symbol
"BU2/U0/i_synth_option.i_synth_model/opt_vx6.i_uniwrap/i_primitive" can be sourced only by ACOUT bus of a different DSP48E1.
ERROR:LIT:594 - BCIN bus of DSP48E1 symbol
"BU2/U0/i_synth_option.i_synth_model/opt_vx6.i_uniwrap/i_primitive" can be sourced only by BCOUT bus of a different DSP48E1.
Errors found during logical drc.

These occur if the user has generated the IP core without enabling IOBs and then implements just the core through the tools using the "-u" switch in MAP to ensure the core is not optimized away.

NOTE: This can happen on Virtex-5 FPGA as well.

Solution

These are valid DRC checks which were previously enabled for Virtex-5 FPGA but need to be ported over to Virtex-6 FPGA and were in ISE 12.1 software.

The user can work around this issue by generating the DSP48 Macro v2.0 core through CORE Generator enabling the IOB pads, i.e. create the "_padded.ngc" file. To do this the user needs to edit their CORE Generator project options by selecting the "Create Netlist Wrapper with I/O pads" option in the Advanced tab. It is then possible to run this wrapped design through the implementation without using the "-u" switch in MAP.

This should not occur when the core is included in a larger design as the "-u" option should not be required.

Please see (Xilinx Answer 33537) for a detailed list of LogiCORE IP DSP48 Macro Release Notes and Known Issues.
AR# 35673
Date Created 08/03/2010
Last Updated 08/04/2010
Status Active
Type General Article
IP
  • DSP48 Macro