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AR# 35675

ML605 - Decoupling for jitter attenuator on PCIe clock


The ML605 Evaluation Kit uses the ICS874001I-05 PCIe Jitter Attenuator from IDT onboard, however, the decoupling used does not match the IDT datasheet.


The ML605 Evaluation Kit uses the ICS874001I-05PCIe JitterAttenuator (U9 in the schematic) datasheet which can be found at:

The power supply filtering recommendation given in the IDT datasheet is as follows:

Article 35675
Article 35675

However, in the ML605 schematics, while VDDA (pin 8) of U9 is connected through a 10 ohm resistor to 3.3V, it is not decoupled at the pin with a 0.01 uF capacitor as the IDT datasheet recommends.

Customers intending to use the ICS874001I-05 in a similar application in their own system should follow the recommendation given in the IDT datasheet above, and not follow the ML605 schematics.

AR# 35675
Date Created 05/13/2010
Last Updated 12/15/2012
Status Active
Type General Article
Boards & Kits
  • Virtex-6 FPGA Connectivity Kit
  • Virtex-6 FPGA Embedded Kit
  • Virtex-6 FPGA ML605 Evaluation Kit