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AR# 35678

ML510 - Newer Boards Shipped with 1 GB DIMM

Description

Newer ML510 Embedded Development Platform boards ship with 1 GB DIMMs versus the 512 MB DIMMs on previous boards.This change is due tothe discontinuation of the 512 MB DIMMs by the memory manufacturer.

ML510 boards with 1 GB DIMMs require the application of the solution detailed below.

Solution

The ML510 Embedded Development Platform boards shipped with 1 GB DIMMs require the application of the following solution. This allows the 1 GB DIMMs to work as the 512 MB DIMM.All previous and future designs will work across boards built with 512 MB and 1 GB DIMMs.

The solution needed is to tie the BA2 pins to a logic zero on designs using MPMC or MIG.

The 512 MB DIMMs are WD2RE512X809-667G-PE
The 1 GB DIMMs on the newer ML510 boards are WD2RE01GX809-667G-PE

All the data sheets can be found on the ML510 web page: http://www.xilinx.com/ml510.

Note: The BA2 pin is not connected to the memory devices on the 512 MB DIMMs, so it has no affect on boards shipped with 512 MB DIMMs.When the BA2 pin is driven low on the 1 GB DIMMs, it makes half of the memory unavailable, that is, the resulting memory is half theoriginalsize.

The next procedure describes how to modify any existing and/or future EDK designs so thatthey can operate with 1 GB DIMMs.The concept is the same for any MIG based design.

DIMM0

1.Add the following to the port section of the MHS file:

PORT fpga_0_DDR2_SDRAM_DIMM0_DDR2_BankAddr_pin_2 = fpga_0_DDR2_SDRAM_DIMM0_DDR2_BankAddr_pin_2, DIR = O

2. Add this core to the very bottom of the MHS file:

BEGIN util_reduced_logic

PARAMETER INSTANCE = AND_Gate_0

PARAMETER C_OPERATION = and

PARAMETER C_SIZE = 2

PARAMETER HW_VER = 1.00.a

PORT Op1 = 0b0 & 0b0

PORT Res = fpga_0_DDR2_SDRAM_DIMM0_DDR2_BankAddr_pin_2

END

3. Add the following to the UCF file:

Net fpga_0_DDR2_SDRAM_DIMM0_DDR2_BankAddr_pin_2 LOC=K39 | IOSTANDARD = SSTL18_II;

DIMM1

1. Add the following to the port section of the MHS file:

PORT fpga_0_DDR2_SDRAM_DIMM1_DDR2_BankAddr_pin_2 = fpga_0_DDR2_SDRAM_DIMM1_DDR2_BankAddr_pin_2, DIR = O

2. Add this core to the very bottom of the MHS file:

BEGIN util_reduced_logic

PARAMETER INSTANCE = AND_Gate_1

PARAMETER C_OPERATION = and

PARAMETER C_SIZE = 2

PARAMETER HW_VER = 1.00.a

PORT Op1 = 0b0 & 0b0

PORT Res = fpga_0_DDR2_SDRAM_DIMM1_DDR2_BankAddr_pin_2

END

3. Add the following to the UCF file:

Net fpga_0_DDR2_SDRAM_DIMM1_DDR2_BankAddr_pin_2 LOC= AH35| IOSTANDARD = SSTL18_II;

Note: The solution above allows the designs for 512 MB DIMM to work for 1 GB DIMM,it makes half of the memory unavailable. To access full 1 GB memory, the Base Address of MPMC instance needs to be modified to 1 GB memory size. And,BA2 pins will not be tiedto a logic zero on designs using MPMC or MIG. It should be connected to external memory DIMM0/DIMM1.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
38095 ML510 - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 35678
Date Created 06/15/2010
Last Updated 12/15/2012
Status Active
Type General Article
Boards & Kits
  • ML510