UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35696

Spartan-6 SSO Limit Table - Noise Margin Relationship

Description

In the Spartan-6 FPGA Data Sheet v3.0 Table 34, why do higher Drive options sometimes have larger SSO values

http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf

Solution

The SSO numbers in Table 32 assume a common IOSTANDARD drive strength for all of the pins, including both the aggressors and the victim.
Higher-drive victims have more noise margin, and therefore, are sometimes better. As a consequence, this table is optimal for those cases where the whole bank is populated by the same IOSTANDARD. For example, LVCMOS33 Slow in Bank 0/2 increases fromone SSO per Vcco/GND pair at 16 mA drive totwo at 24 mA drive.

In general, for a given pin, reducing the Drive level and/or the Slew rate of other pins in the bank will improve the SSO characteristics.

For all other cases, PlanAhead software 12.4 and later versions handle mixed standards.

AR# 35696
Date Created 05/17/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT