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AR# 35742

MIG v3.0-3.4 Virtex-6 DDR2 SDRAM - Incorrect timing on DDR2_RAS_N


The MIG Virtex-6 DDR2 design uses IODELAYs with tap count set to 0 in the output path of all DDR2 control/address outputs in order to match the output path delay between these signals and the forwarded clock to the DRAM. However, an error exists in the code where the DDR2_RAS_N output does not have an IODELAY in the its output path. As a result, its output path delay will be faster than that of the forwarded clock by up to 1.5 ns in the worst case. This can cause setup or hold violations at the DRAM for RAS_N timing.


The HDL file PHY_CONTROL_IO.V/.VHD must be modified to correctly instantiate the IODELAY in the RAS_N output path. Updated Verilog and VHDL versions of this file are available from the link below:

This issue will be resolved in MIG 3.5, which will be available with ISE tools 12.2.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 35742
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
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  • Virtex-6 LXT
  • Virtex-6 SXT
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  • MIG
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