We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35748

Design Assistant for PCI Express - Incorrect use of trn_trem_n could cause malformed TLPs to get transferred


User applications must ensure that trn_trem_n is set correctly to avoid transmitting malformed TLPs.

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.


Refer to the user guides for information on how to correctly use trn_trem_n during packet transmission. This signal is used to inform the core how much data is valid on the end of frame cycle. To find the correct user guide, see (Xilinx Answer 35920). By not using this signal correctly, it may cause a TLP with a payload that does not match the length placed in the TLP header. In some cases, this may get transmitted to the link partner which would cause a fatal error condition to occur, possibly hanging the system.

Revision History
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

AR# 35748
Date Created 08/06/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Endpoint Block Plus Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )