We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35775

Serial RapidIO - How much power does the Serial RapidIO solution consume?


The power consumed by the Serial RapidIO Core is highly dependent on the device chosen, toggle rates of the design and Core parameters such as clock frequency, line rate, number of lanes, etc. It is possible, however, to use the XPower Estimator (XPE) spreadsheets to obtain a general estimate of the power consumed by the SRIO Core. This article outlines the steps needed to do this, as well as an example of a populated spreadsheet and its results using the Serial RapidIO v5.5 Core on a Virtex-6 device.


To estimate the power used by the Serial RapidIO Core, perform the following:
  1. Generate the Core in Coregen and specify the correct settings required for your design.
  2. Remove the Chipscope Cores from the example design by changing the SRIO_VIO parameter from "1" to "0" in the top level of the example design called: "core_name"_top.v(hd).
  3. Double-click the implement.bat file to run the example design through implementation.
  4. Download and launch the XPE spreadsheet from the "Power Solutions" website.
  5. Input the correct settings for your device into the spreadsheet.
  6. Import the MAP results (mapped.mrp) from implementation by using the Import button on the first page of the spreadsheet.
  7. Adjust toggle rates and other settings as needed to match your expected use.
  8. View power results on page 1 of the spreadsheet

Example Results:

The following results were obtained by using the above steps with the Serial RapidIO v5.5 Core and targeting a XC6VLX240T. The core used was x4 lanes running at 3.125 Gb/s with a 125 MHz reference clock. The Static Power shown is the power consumed by the device regardless of the design that is loaded into the device while the power consumed by the clocking, logic, block RAM, I/Os, and transceivers is the power consumed by the actual Serial RapidIO Core and the accompanying example design. For this example, we chose a toggle rate of 12.5% as a typical value and 25% as a max value. Although these are design dependent, these values are often used for a typical and worst case estimate. The completed example spreadsheet can be downloaded.
Toggle Rate = 12.5%
Toggle Rate = 25%
Power consumed by clocking, logic, BRAMs and I/Os
294 (mW) 390 (mW)
Power consumed by transceivers
614 (mW)
614 (mW)
Total power consumed by Core and Example Design
908 (mW)
1.004* (W)
Static power**
2.409 (W)
2.412 (W)
Total power when running on device
3.316 (W)
3.416 (W
*Note that the small increase in static power from 12.5% to 25% is due to the small increase in junction temperature estimated after increasing the toggle rate.
**Static power (leakage) is the power consumed by the device regardless of the design loaded, this is not power consumed due to the SRIO Core itself.
AR# 35775
Date Created 06/25/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Serial RapidIO