35781

If the DCM/PLL/MMCM is configured as external feedback, how do you simulate it?

To simulate external feedback you can add the external board delay in the testbench.

For VHDL: the keyword "transport" should be used in testbench. FBIN <= transport FBOUT after 1ns;

For Verilog: assign FBIN = #1ns FBOUT;

Associated Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
46790	Spartan-6 FPGA Design Assistant - Troubleshooting Common Clocking Problems	N/A	N/A

AR# 35781
Date Created	08/10/2010
Last Updated	03/07/2013
Status	Active
Type	General Article
Devices	Spartan-3 Spartan-3E Spartan-3A More Spartan-6 LX Spartan-6 LXT Virtex-4 LX Virtex-4 FX Virtex-4 QPro/R Virtex-4 SX Virtex-5 FXT Virtex-5 LX Virtex-5 LXT Virtex-5 SXT Virtex-5 TXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT Spartan-3A DSP Spartan-3AN Less
IP	Digital Clock Manager (DCM) Module PLL Module

AR# 35781 How to do simulation on DCM/PLL/MMCM with external feedback?

Description

Solution

Linked Answer Records

Associated Answer Records

Actions

All Programmable Technologies and Devices

New Connectivity Kit for High-Bandwidth and High-Performance Applications

Mobile Access for Forums

Kintex-7 FPGA KC705 Evaluation Kit

All Programmable Technologies and Devices

AR# 35781 How to do simulation on DCM/PLL/MMCM with external feedback?

Description

Solution

Linked Answer Records

Associated Answer Records

Actions