This section of the MIG Design Assistant focuses on Read Latency of the Virtex-6 DDR3/DDR2 designs. See below to find information related to your specific question.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
The number of commands already in the pipeline before the read command is issued
Whether an ACTIVATE command needs to be issued to open the new bank/row
Whether a PRECHARGE command needs to be issued to close a previously opened Bank
Specific timing parameters for the memory, such as TRAS and TRCD in conjunction with the bus clock frequency
Commands can be interrupted, and banks/rows can forcibly be closed when the periodic AUTO REFRESH command is issued
For specific values in clock cycles and a further description of Read Latency for Virtex-6 DDR3/DDR2 designs, please refer to the "Virtex-6 FPGA Memory Interface Solutions" User Guide UG406, section "Read Latency: