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AR# 35836

LogiCORE IP 10-Gigabit Ethernet MAC - Timing errors seen when targeting Virtex-4 FPGAs


In v8.5 and later of the LogiCORE IP 10-Gigabit Ethernet MAC, timing errors have been experienced in some Virtex-4 FPGA FPGA implementations.


To resolve these errors, try removing the -timing switch from MAP or try using AREA_GROUP constraints. 

If timing failures are still encountered, open a webcase with Xilinx Technical Support to further explore a solution.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
35244 LogiCORE IP 10-Gigabit Ethernet MAC v10.1 - Release Notes and Known Issues for ISE Design Tools 12.1 N/A N/A
AR# 35836
Date Created 05/26/2010
Last Updated 05/26/2014
Status Archive
Type General Article
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 SX
  • ISE Design Suite - 12.1
  • ISE Design Suite - 11.1
  • ISE - 10.1
  • 10 Gigabit Ethernet Media Access Controller