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AR# 35852 12.1 EDK, xps_timebase_wdt_v1_01_a - WDT_RESET output may combinatorially glitch

When using the XPS Timebase WDT core, the WDT_RESET output may glitch, potentially triggering unexpected behavior when driving asynchronous logic. How do I resolve this issue?

Consider synchronizing the WDT_RESET signal before driving to any asynchronous logic. This can be accomplished by registering WDT_RESET with a single flip-flop in the PLB clock domain.

For single-clock domains, WDT_RESET should be consumed by synchronous logic, which will filter out any spurious pulses by standard timing analysis.

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AR# 35852
Date Created	05/28/2010
Last Updated	05/28/2010
Status	Active
Type
Devices	Spartan-3 Spartan-3 XA Spartan-3A More Spartan-3A DSP Spartan-3AN Spartan-3E Spartan-6 LX Spartan-6 LXT Virtex-4 FX Virtex-4 LX Virtex-4 QPro/R Virtex-4 SX Virtex-5 FXT Virtex-5 LX Virtex-5 LXT Virtex-5 SXT Virtex-5 TXT Virtex-5Q Virtex-6 CXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Less
Tools	EDK - 10.1 sp2 EDK - 10.1 EDK - 10.1 sp1 More EDK - 10.1 sp3 EDK - 11.1 EDK - 11.2 EDK - 11.3 EDK - 11.4 EDK - 11.5 EDK - 12.1 EDK - 8.1i EDK - 8.1i sp1 EDK - 8.1i sp2 EDK - 8.1i sp3 EDK - 8.2i EDK - 8.2i sp1 EDK - 8.2i sp2 EDK - 8.2i sp3 EDK - 9.1i EDK - 9.1i sp1 EDK - 9.1i sp2 EDK - 9.1i sp3 EDK - 9.2i EDK - 9.2i sp1 EDK - 9.2i sp2 EDK - 9.2i sp3 EDK - 9.2i sp4 EDK - Legacy Less
IP	XPS Timebase Watchdog Timer

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