We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35917

PlanAhead - Importing placement into a Virtex-6 FPGA design indicates that BUFGDLL is not a supported primitive


When I import placement in PlanAhead for a Virtex-6 FPGA design, I receive a message that BUFGDLL is an unrecognized primitive.

Why does this happen? How do I work around it?


BUFGDLL is not a supported primitive for Virtex-6 FPGA designs.

This netlist in this case must have been retargeted from a previous architecture.

To eliminate this error, edit your code and netlist to include only supported primitives.

AR# 35917
Date Created 05/27/2010
Last Updated 08/11/2014
Status Active
Type General Article
  • PlanAhead - 12.1