We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35954

Virtex-5 - USERCLKO and CCLK not synchonised in STARTUP_VIRTEX5 when accessing SPI Flash


In XAPP1020, we access configuration SPI Flash by usingSTARTUP_VIRTEX5. But, the input ofSTARTUP_VIRTEX5 USERCLKO is not synchronous with output CCLK from the beginning.


This is the connection in XAPP1020.

And we assume that the outputSCK (Which is CCLK) will follow the inputUSRCCLKO.However, after configuration theCCLK will keep high no matter what the initial state ofUSRCCLKO. These two signals willbe synchronousonly after the first falling edge ofUSRCCLKO.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
52626 7 Series, STARTUPE2 - USRCCLK0 requires three clock cycles to switch CCLK output to User Function N/A N/A
AR# 35954
Date 10/26/2012
Status Active
Type Known Issues
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Less
Page Bookmarked