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AR# 35954 Virtex-5 - USERCLKO and CCLK not synchonised in STARTUP_VIRTEX5 when accessing SPI Flash

Description

In XAPP1020, we access configuration SPI Flash by usingSTARTUP_VIRTEX5. But, the input ofSTARTUP_VIRTEX5 USERCLKO is not synchronous with output CCLK from the beginning.

Solution

This is the connection in XAPP1020.


And we assume that the outputSCK (Which is CCLK) will follow the inputUSRCCLKO.However, after configuration theCCLK will keep high no matter what the initial state ofUSRCCLKO. These two signals willbe synchronousonly after the first falling edge ofUSRCCLKO.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
52626 7-Series - STARTUPE2_USRCCLK0 ignores first two clock cycles at output N/A N/A

Actions

AR# 35954
Date Created 12/16/2011
Last Updated 10/26/2012
Status Active
Type Known Issues
Devices
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
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