Speedprint provides general information about block delays in the given device.
How can we interpret the delays corresponding to a delay name?
Let us use an example to understand:
Prior to Multi-Corner Multi-Nodeanalysis:-
The delay name is followed by a pair of values representing a relative minimum delay value and its corresponding maximum value.
If a range of values exists for a delay name, then the smallest pair and the largest pair are reported.
Tdick (268.00 / 268.00) (1501.00 / 1501.00)
Including Multi-Corner Multi-NodeAnalysis:-
The delay name is followed by sets of pair values representing the minimum delay value and maximum delay value for each process (Fast, Slow).
T_timing_delay_name (Fast_min, Fast_max) (Slow_min, Slow_max)
Tdick (85/85, 306/306) (210/210, 778/778)
Here is how the Tdick can be interpreted while being implemented in the FPGA.
We can see that there are two different paths for the same delay element name.
One goes from BX => XQ
The other goes from BY=> YQ
So one set of values correspond to BX -> XQ and the other set of values correspond to BY -> YQ.